Referring to FIG. 1, a block diagram of a conventional double diode electrostatic discharge (ESD) circuit 20 is shown. The double diodes 22 and 24 are an effective ESD protection scheme for an analog circuit 26 and are widely used. For a positive ESD zap at a pad 28 with respect to power rails 30 and 32, current passes from the pad 28 through the diode 22, the rail 30, a power clamp 34 and to the rail 32. For a negative ESD zap at the pad 28 with respect to the rail 32, current passes from the rail 30 through the power clamp 34, the rail 32, the diode 24 and to the pad 28.
The double diode approach does not work for some applications. A High-Definition Multimedia Interface (HDMI) (HDMI® is a registered trademark of HDMI Licensing, LLC, Sunnyvale, Calif.) includes a compliance test that specifies a minimum leakage from the pad 28 to either rail 30 or 32 while the system is powered down (i.e., rail 30=0 volts). However, a significant current can leak through the diode 22 to the rail 30 when system is powered down and a positive voltage is present at the pad 28.
Referring to FIG. 2, a block diagram of a conventional N-channel Field Effect Transistor (NFET) ESD circuit 40 is shown. To solve the powered-down leakage problem of the circuit 20, a silicide blocked NFET 42 is used to snap back during an ESD event to protect the circuit 26. Since no current path exists between the pad 28 and the rail 30, current leakage will not occur even when system is powered down. However, the NFET approach is hard to make work and ESD performance is usually poor.
During a positive ESD zap with respect to the rail 32, current goes through silicide blocked NFET 42 directly to the rail 32. For a positive ESD zap with respect to the rails 30 and 32, current goes through NFET 42 to the rail 32, a diode 44 and to the rail 30. During a negative ESD zap with respect to the rail 32, current goes from the rail 32 through a diode 46 to the pad 28. For a negative ESD zap with respect to the rail 30, current goes from the rail 30, through the power clamp 34, the rail 32, the diode 46 and to the pad 28.
Unlike the circuit 20, the circuit 40 has no DC path from the pad 28 to either rail 30 or 32. Therefore, no current leakage issue exists while the rail 30 is powered down. The ESD performance of circuit 40 depends on how fast NFET 42 achieves the snap back mode. Usually the turn on voltage of the NFET 42 is close to 10 volts. Hence, the ESD performance of the circuit 40 is weaker than the circuit 20 for the same device size.